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flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 1 document title 16m bit (2m x8/1m x16) dual bank nor flash memory revision history revision no. 0.0 remark advance history initial draft draft date july 25, 2004
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 2 16m bit (2m x8/1m x16) du al bank nor flash memory the k8d1716u featuring single 3.0v power supply, is a 16mbit nor-type flash memory organiz ed as 2mx8 or 1m x16. the memory architecture of the device is designed to divide its memory arrays into 39 blocks to be protected by the block group. this block architecture pr ovides highly flexible erase and program capability. the k8d1716u nor flash consists of two banks. this device is capable of reading data from one bank while programming or erasing in the other bank. access times of 70ns, 80ns and 90ns are available for the device. the device s fast access times allow high speed microprocessors to operate without wait states. the device performs a program operation in units of 8 bits (byte) or 16 bits (word) and erases in units of a block. single or multiple blocks can be erased. the block erase operation is completed within typically 0.7 sec. the device requires 15ma as program/erase current in the standard and industrial temperature ranges. the k8d1716u nor flash memory is created by using sam- sung's advanced cmos proces s technology. this device is available in 48 pin tsop1 package. the device is compatible with eprom applications to require high-density and cost- effective nonvolatile read/write storage solutions. features ? single voltage, 2.7v to 3.6v for read and write operations ? organization 1,048,576 x 16 bit (word mode) ? fast read access time : 70ns ? read while program/erase operation ? dual bank architectures bank 1 / bank 2 : 8mb / 8mb ? secode(security code) bl ock : extra 64k byte block ? power consumption (typical value @5mhz) - read current : 14ma - program/erase current : 15ma - read while program or read while erase current : 25ma - standby mode/auto sleep mode : 5 a ? wp /acc input pin - allows special protection of two outermost boot blocks at v il , regardless of block protect status - removes special protection of two outermost boot block at v ih, the two blocks return to normal block protect status - program time at v hh : 9 s/word ? erase suspend/resume ? unlock bypass program ? hardware reset pin ? command register operation ? block group protection / unprotection ? supports common flash memory interface ? industrial temperature : -40 c to 85 c ? endurance : 100,000 program/erase cycles minimum ? data retention : 10 years ? package : 48 pin tsop1 : 12 x 20 mm / 0.5 mm pin pitch general description samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin description pin name pin function a0 - a19 address inputs dq0 - dq14 data inputs / outputs dq15/a-1 dq15 data input / output a-1 lsb address byte word / byte selection ce chip enable oe output enable reset hardware reset pin ry/by ready/busy output we write enable wp /acc hardware write protection/program acceleration vcc power supply v ss ground n.c no connection pin configuration 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 n.c we reset n.c wp /acc ry/by a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe vss ce a0 note : please refer to the package dimension.
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 3 functional block diagram vcc vss ce oe we byte reset ry/by a0~a19 dq0~dq14 i/o interface & bank control x dec y dec latch & control latch & control dec x y dec erase control program control high voltage gen. bank2 cell array bank1 address bank2 address bank1 data-in/out bank2 data-in/out bank1 cell array wp /acc dq15/a-1
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 4 ordering information k 8 d 17 1 6 u t b - t i 0 7 samsung nor flash memory device type dual bank boot block operating temperature range c = commercial temp. (0 c to 70 c) i = industrial temp. (-40 c to 85 c) block architecture t = top boot block b = bottom boot block version b = 3rd generation access time 07 = 70 ns 08 = 80 ns 09 = 90 ns operating voltage range 2.7v to 3.6v package y = 48 tsop1 organization x16 table 1. product line-up part no. - 7 -8 -9 vcc 2.7v~3.6v max. address access time (ns) 70ns 80ns 90ns max. ce access time (ns) 70ns 80ns 90ns max. oe access time (ns) 25ns 25ns 35ns table 2. k8d1716u d evice bank divisions device part number bank 1 bank 2 mbit block sizes mbit block sizes k8d1716u 8 mbit eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword 8 mbit sixteen 64 kbyte/32 kword bank division 17 = 8mbits + 8mbits
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 5 table 3. top boot block address (k8d1716ut ) k8d1716ut block a19 a18 a17 a16 a15 a14 a13 a12 block size (kw/kb) address range word mode byte mode bank1 ba3811111111 4 / 8 ff 000h-fffffh 1fe000h-1fffffh ba3711111110 4 / 8 fe 000h-fefffh 1fc000h-1fdfffh ba3611111101 4 / 8 fd 000h-fdfffh 1fa000h-1fbfffh ba3511111100 4 / 8 fc 000h-fcfffh 1f8000h-1f9fffh ba3411111011 4 / 8 fb 000h-fbfffh 1f6000h-1f7fffh ba3311111010 4 / 8 fa 000h-fafffh 1f4000h-1f5fffh ba3211111001 4 / 8 f 9000h-f9fffh 1f2000h-1f3fffh ba3111111000 4 / 8 f 8000h-f8fffh 1f0000h-1f1fffh ba30 1 1 1 1 0 x x x 32 / 64 f0000h-f7fffh 1e0000h-1effffh ba29 1 1 1 0 1 x x x 32 / 64 e8000h-effffh 1d0000h-1dffffh ba28 1 1 1 0 0 x x x 32 / 64 e0000h-e7fffh 1c0000h-1cffffh ba27 1 1 0 1 1 x x x 32 / 64 d8000h-dffffh 1b0000h-1bffffh ba26 1 1 0 1 0 x x x 32 / 64 d0000h-d7fffh 1a0000h-1affffh ba25 1 1 0 0 1 x x x 32 / 64 c8000h-cffffh 190000h-19ffffh ba24 1 1 0 0 0 x x x 32 / 64 c0000h-c7fffh 180000h-18ffffh ba23 1 0 1 1 1 x x x 32 / 64 b8000h-bffffh 170000h-17ffffh ba22 1 0 1 1 0 x x x 32 / 64 b0000h-b7fffh 160000h-16ffffh ba21 1 0 1 0 1 x x x 32 / 64 a8000h-affffh 150000h-15ffffh ba20 1 0 1 0 0 x x x 32 / 64 a0000h-a7fffh 140000h-14ffffh ba19 1 0 0 1 1 x x x 32 / 64 98000h-9ffffh 130000h-13ffffh ba18 1 0 0 1 0 x x x 32 / 64 90000h-97fffh 120000h-12ffffh ba17 1 0 0 0 1 x x x 32 / 64 88000h-8ffffh 110000h-11ffffh ba16 1 0 0 0 0 x x x 32 / 64 80000h-87fffh 100000h-10ffffh bank2 ba15 0 1 1 1 1 x x x 32 / 64 78000h-7ffffh 0f0000h-0fffffh ba14 0 1 1 1 0 x x x 32 / 64 70000h-77fffh 0e0000h-0effffh ba13 0 1 1 0 1 x x x 32 / 64 68000h-6ffffh 0d0000h-0dffffh ba12 0 1 1 0 0 x x x 32 / 64 60000h-67fffh 0c0000h-0cffffh ba11 0 1 0 1 1 x x x 32 / 64 58000h-5ffffh 0b0000h-0bffffh ba10 0 1 0 1 0 x x x 32 / 64 50000h-57fffh 0a0000h-0affffh ba9 0 1 0 0 1 x x x 32 / 64 48000h-4ffffh 090000h-09ffffh ba8 0 1 0 0 0 x x x 32 / 64 40000h-47fffh 080000h-08ffffh ba7 0 0 1 1 1 x x x 32 / 64 38000h-3ffffh 070000h-07ffffh ba6 0 0 1 1 0 x x x 32 / 64 30000h-37fffh 060000h-06ffffh ba5 0 0 1 0 1 x x x 32 / 64 28000h-2ffffh 050000h-05ffffh ba4 0 0 1 0 0 x x x 32 / 64 20000h-27fffh 040000h-04ffffh ba3 0 0 0 1 1 x x x 32 / 64 18000h-1ffffh 030000h-03ffffh ba2 0 0 0 1 0 x x x 32 / 64 10000h-17fffh 020000h-02ffffh ba1 0 0 0 0 1 x x x 32 / 64 08000h-0ffffh 010000h-01ffffh ba0 0 0 0 0 0 x x x 32 / 64 00000h-07fffh 000000h-00ffffh device block address a19-a12 block size (x8) address range (x16) address range k8d1716ut 11111xxx 64/32 1f 0000h-1fffffh f8000h-fffffh table 4. secode block addresses for top boot devices
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 6 table 5. bottom boot block address (k8d1716ub ) k8d1716ut block a19 a18 a17 a16 a15 a14 a13 a12 block size (kw/kb) address range word mode byte mode bank2 ba3811111xxx 32 / 64f8000h-fffffh1f 0000h-1fffffh ba3711110xxx 32 / 64 f 0000h-f7fffh 1e0000h-1effffh ba3611101xxx 32 / 64e8000h-e ffffh 1d0000h-1dffffh ba3511100xxx 32 / 64e 0000h-e7fffh 1c0000h-1cffffh ba3411011xxx 32 / 64d8000h-dffffh1b 0000h-1bffffh ba3311010xxx 32 / 64d 0000h-d7fffh 1a0000h-1affffh ba3211001xxx 32 / 64c8000h-cffffh19 0000h-19ffffh ba3111000xxx 32 / 64c 0000h-c7fffh 180000h-18ffffh ba3010111xxx 32 / 64b8000h-b ffffh 170000h-17ffffh ba2910110xxx 32 / 64b 0000h-b7fffh 160000h-16ffffh ba2810101xxx 32 / 64a8000h-a ffffh 150000h-15ffffh ba2710100xxx 32 / 64a 0000h-a7fffh 140000h-14ffffh ba2610011xxx 32 / 64 98000h-9ffffh 130000h-13ffffh ba2510010xxx 32 / 64 9 0000h-97fffh 120000h-12ffffh ba2410001xxx 32 / 64 88000h-8ffffh 110000h-11ffffh ba2310000xxx 32 / 64 8 0000h-87fffh 100000h-10ffffh bank1 ba2201111xxx 32 / 64 78000h-7ffffh 0f0000h-0fffffh ba2101110xxx 32 / 64 7 0000h-77fffh 0e0000h-0effffh ba2001101xxx 32 / 64 68000h-6ffffh 0d0000h-0dffffh ba1901100xxx 32 / 64 6 0000h-67fffh 0c0000h-0cffffh ba1801011xxx 32 / 64 58000h-5ffffh 0b0000h-0bffffh ba1701010xxx 32 / 64 5 0000h-57fffh 0a0000h-0affffh ba1601001xxx 32 / 64 48000h-4ffffh 090000h-09ffffh ba1501000xxx 32 / 64 4 0000h-47fffh 080000h-08ffffh ba1400111xxx 32 / 64 38000h-3ffffh 070000h-07ffffh ba1300110xxx 32 / 64 3 0000h-37fffh 060000h-06ffffh ba1200101xxx 32 / 64 28000h-2ffffh 050000h-05ffffh ba1100100xxx 32 / 64 2 0000h-27fffh 040000h-04ffffh ba1000011xxx 32 / 64 18000h-1ffffh 030000h-03ffffh ba9 00010xxx 32 / 64 1 0000h-17fffh 020000h-02ffffh ba8 00001xxx 32 / 64 08000h-0ffffh 010000h-01ffffh ba7 00000111 4 / 8 0 7000h-07fffh 00e000h-00ffffh ba6 00000110 4 / 8 0 6000h-06fffh 00c000h-00dfffh ba5 00000101 4 / 8 0 5000h-05fffh 00a000h-00bfffh ba4 00000100 4 / 8 0 4000h-04fffh 008000h-009fffh ba3 00000011 4 / 8 0 3000h-03fffh 006000h-007fffh ba2 00000010 4 / 8 0 2000h-02fffh 004000h-005fffh ba1 00000001 4 / 8 0 1000h-01fffh 002000h-003fffh ba0 00000000 4 / 8 0 0000h-00fffh 000000h-001fffh device block address a19-a12 block size (x8) address range (x16) address range k8d1716ub 00000xxx 64/32 000000h-00ffffh 00000h-07fffh table 6. secode block addresses for bottom boot devices
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 7 product introduction table 7. operations table operation ce oe we byte wp / acc a9 a6 a1 a0 dq15/ a-1 dq8/ dq14 dq0/ dq7 reset read word l l h h l/h a9 a6 a1 a0 dq15 d out d out h byte l l h l a9 a6 a1 a0 a-1 high-z d out h stand-by vcc 0.3v x x x (2) x x x x high-z high-z high-z (2) output disable l h h x l/h x x x x high-z high-z high-z h reset x x x x l/h x x x x high-z high-z high-z l write word l h l h (4) a9 a6 a1 a0 d in d in d in h byte l h l l a9 a6 a1 a0 a-1 high-z d in h enable block group protect (3) lhlxl/hxlhl x x d in v id enable block group unprotect (3) lhlx(4)xhhl x x d in v id temporary block group xxxx(4)xxxx x x x v id auto select manufacturer id (5) llhxl/hv id lll x x code (see table 9) h auto select device code (5) llhxl/hv id llh x x code (see table 9) h notes : 1. l = v il (low), h = v ih (high), v id = 8.5v~12.5v, d in = data in, d out = data out, x = don't care. 2. wp /acc and reset pin are asserted at vcc 0.3 v or vss 0.3 v in the stand-by mode. 3. addresses must be composed of the block address (a12 - a19). the block protect and unprotect operations may be implemented via programming equipment too. refer to the "block group protection and unprotection". 4. if wp /acc = v il, the two outermost boot blocks is protected. if wp /acc = v ih, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the met hod described in "block group protection and unprotection". if wp /acc = v hh , all blocks will be temporarily unprotected. 5. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 9. the k8d1716u is a 16mbit (16,777,216 bits) nor-type flash memo ry. the device features singl e voltage power supply operating within the range of 2.7v to 3.6v. the device is programmed by using the channel hot electron (c he) injection mechanism which is used to program eproms. the device is eras ed electrically by using fo wler-nordheim tunneling mechani sm. to provide highly flex- ible erase and program capability, the device adapts a block memory architecture that divides its memory array into 39 blocks ( 64- kbyte x 31 , 8-kbyte x 8). programming is done in units of 8 bits (byte) or 16 bits (word). all bits of data in one or multiple blocks can be erased simultaneously when the device execut es the erase operation. to prevent the device from accidental erasing or over-wr it- ing the programmed data, 39 memory blocks can be hardware protec ted by the block group. byte/wor d modes are available for read operation. these modes can be selected via byte pin. the device provides read access times of 70ns, 80ns and 90ns supporting high speed microprocessors to oper ate without any wait states. the command set of k8d1716u is fully compatible with standar d flash devices. the device is controlled by chip enable (ce ), output enable (oe ) and write enable (we ). device operations are executed by select ive command codes. the command codes to be com- bined wih addresses and data are sequentially written to t he command registers using mi croprocessor write timing. the command codes serve as inputs to an internal state machine which controls the program/erase ci rcuitry. register contents also internall y latch addresses and data necessary to execute the program and erase oper ations. the k8d1716u is implemented with internal program/ erase algorithms to execute the program/erase operations. the in ternal program/erase algorithms are invoked by program/erase command sequences. the internal program algor ithm automatically programs and verifies data at specified addresses. the internal erase algorithm automatically pre-programs the memory cell whic h is not programmed and then executes the erase operation. the k8d1716u has means to indicate the status of completion of pr ogram/erase operations. the status can be indicated via the ry/by pin, data polling of dq7, or the toggle bit (dq6). once the operati ons have been completed, the device automatically resets itself to the read mode. the device requires only 14 ma as acti ve read current and 15 ma for program/erase operations.
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 8 command definitions the k8d1716u operates by selecting and executing its operat ional modes. each operational mode has its own command set. in order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg- ister. writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. the defined valid register command sequences are stated in table 8. note that erase suspend (b0h) and erase resume (30h) commands are valid only while the bl ock erase operation is in progress. table 8. command sequences command sequence cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle word byte word byte word byte word byte word byte word byte read addr 1 ra data rd reset addr 1 xxxh data f0h autoselect manufacturer i d ( 2, 3 ) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah da/ x00h da/ x00h data aah 55h 90h ech autoselect device code (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah da/ x01h da/ x02h data aah 55h 90h (see table 9) autoselect block group protect verify (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah ba / x02h ba/ x04h data aah 55h 90h (see table 9) auto select secode block factory protect verify (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah da / x03h da/ x06h data aah 55h 90h (see table 9) enter secode b l o c k r e g i o n addr 3 555h aaah 2aah 555h 555h aaah data aah 55h 88h exit secode b l o c k r e g i o n addr 4 555h aaah 2aah 555h 555h aaah xxxh data aah 55h 90h 00h program addr 4 555h aaah 2aah 555h 555h aaah pa data aah 55h a0h pd unlock bypass addr 3 555h aaah 2aah 555h 555h aaah data aah 55h 20h unlock bypass program addr 2 xxxh pa data a0h pd unlock bypass reset addr 2 xxxh xxxh data 90h 00h chip erase addr 6 555h aaah 2aah 555h 555h aaah 555h aaah 2aah 555h 555h aaah data aah 55h 80h aah 55h 10h block erase addr 6 555h aaah 2aah 555h 555h aaah 555h aaah 2aah 555h ba data aah 55h 80h aah 55h 30h block erase suspend (4, 5) addr 1 xxxh data b0h block erase resume addr 1 xxxh data 30h cfi query (6) addr 1 55h aah data 98h
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 9 notes : 1. ra : read address, pa : program address, rd : read data, pd : program data da : dual bank address, ba : block address (a12 - a19), x = don?t care . 2. to terminate the autoselect mode, it is necessary to write reset command to the register. 3. the 4th cycle data of autoselect mode is output data. the 3rd and 4th cycle bank addresses of autoselect mode must be same. 4. the read / program operations at n on-erasing blocks and the autoselect mode are allowed in the erase suspe nd mode. 5. the erase suspend co mmand is applicable only to the block erase operation. 6. command is valid when the device is in read mode or autoselect mode. 7. dq8 - dq15 are don?t care in command sequence, but rd and pd is excluded. 8. a11 - a19 are also don?t care, except for the case of special notice. description ce oe we a19 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 byte =v ih byte =v il manufacturer id l l h da x v id xl x ll x x ech device code k8d1716ut (top boot block) llhdaxv id x l x l h 22h x a0h device code k8d1716ub (bottom boot block) llhdaxv id x l x l h 22h x a2h block protection verification llhbaxv id xl xhl x x 01h (protected), 00h (unprotected) secode block (2) indicator bit (dq7) llhdaxv id xl xhh x x 80h (factory locked), 00h (not factory locked) table 9. k8d1716u autoselect codes, (high voltage method) notes : 1. l=logic low=v il , h=logic high=v ih , da=dual bank address, ba=block address, x=don?t care . 2. secode block : security code block.
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 10 device operation byte/word mode if the byte pin is set at logical "1" , the device is in wo rd mode, dq0-dq15 are active. otherwise the byte pin is set at logical "0" , the device is in byte mode, dq0-dq7 are active. dq8-dq14 are in the high-z state and dq15 pin is used as an input for the lsb (a-1) address pin. read mode the k8d1716u is controll ed by chip enable (ce ), output enable (oe ) and write enable (we ). when ce and oe are low and we is high, the data stored at the specifi ed address location,will be the output of the device. the outputs are in high impedance state whenever ce or oe is high. standby mode the k8d1716u features stand-by mode to reduce power consumption. this mode puts the device on hold when the device is dese- lected by making ce high (ce = v ih ). refer to the dc characteristics for more details on stand-by modes. output disable the device outputs are disabled when oe is high (oe = v ih ). the output pins are in high impedance state. automatic sleep mode k8d1716u features automatic sleep mode to minimize the devi ce power consumption. since the device typically draws 5 a of the current in automatic sleep mode, this feat ure plays an extremely important role in battery-powered applications. when addresses remain steady for t aa +50ns, the device automatically activates the automati c sleep mode. in the sleep mode, output data is latched and always available to the system. when addresses are change d, the device provides new data without wait time. data outputs t aa + 50ns data auto sleep mode address data data data data figure 1. auto sleep mode operation autoselect mode the k8d1716u offers the autoselect mode to identify manufacture r and device type by reading a binary code. the autoselect mode allows programming equipment to automatica lly match the device to be programmed with its corresponding programming algorithm. in addition, this mode allows the verification of the status of write protected blocks. this mode is used by two method. the on e is high voltage method to be required v id (8.5v~12.5v) on address pin a9. when a9 is held at v id and the bank address or block address is asserted, the device outputs the valid data vi a dq pins(see table 9 and figure 2). the re st of addresses except a0, a1 and a6 a re don t care. the other is autoselect command method that the aut oselect code is acce ssible by the commamd sequence without v id. the manufacturer and device code may also be read via the command register. the command sequence is shown in table 8 and figure 3. the autoselect operation of block protect verification is initiated by first writing two unlock cycle. the third cycl e must con- tain the bank address and autoselect command (90h). if block addres s while (a6, a1, a0) = (0,1,0) is finally asserted on the ad dress pin, it will produce a logical "1" at the device output dq0 to i ndicate a write protected block or a logical "0" at the device output dq0 to indicate a write unprotected block. to terminate the autoselect operation, write reset command (f0h) into the command regis ter.
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 11 figure 3. autoselect operation ( by command sequence method ) we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h 90h 00h/ 01h/ ech manufacturer code device code a19 a0(x16)/* dq15 dq0 f0h return to read mode write (program/erase) mode the k8d1716u executes its program/erase operations by writing commands into the command register. in order to write the com- mands to the register, ce and we must be low and oe must be high. addresses are latched on the falling edge of ce or we (which- ever occurs last) and the data are latched on the rising edge of ce or we (whichever occurs first) . the device uses standard microprocessor write timing. program the k8d1716u can be programmed in units of a word or a byte. progr amming is writing 0's into the memory array by executing the internal program routine. in order to perform the internal pr ogram routine, a four-cycle command sequence is necessary. the fir st two cycles are unlock cycles. t he third cycle is assigned for the program setup command. in the last cycle, the address of the mem- ory location and the data to be programmed at that location are written. the device automatically generates adequate program pulses and verifies the programmed cell marg in by the internal program routine. during the execution of the routine, the system is not required to provide furt her controls or timings. during the internal program routine, commands written to the devi ce will be ignored. note that a hardware reset during a progra m operation will cause data corruptio n at the corresponding location. figure 4. program command sequence we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h a0h program program program start dq15-dq0 address data ry/by a9 v id 00h 01h ech 22a0h or 22a2h manufacturer code device code a6,a1,a0* dq15-dq0 figure 2. autoselect operation ( by high voltage method ) return to read mode v = v ih or v il 22a0h or 22a2h note : the addresses other than a0 , a1 and a6 are don t care. please refer to table 9 for device code. note : the 3rd cycle and 4th cycle address must include the sa me bank address. please refer to table 9 for device code. ( k8d1716u ) (k8d1716u) a19 a-1(x8) a19 a0(x16)/ a19 a-1(x8) 00h 02h
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 12 unlock bypass the k8d1716u provides the unlock bypass mode to save its program time for program oper ation. the mode is invoked by the unlock bypass command sequence. then, the unlock bypass program command sequence is required to program the device. unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence comprises only two bus cycles. the unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. writ- ing first two unlock cycles is followed by a third cycle containing the unl ock bypass command (20h). once the device is in the unlock bypass mode, the unlock bypass program command sequence is nec essary to program in this mode. the unlock bypass program command sequence is comprised of only two bus cyc les; writing the unlock bypass program command (a0h) is followed by the pro- gram address and data. this command sequence is the only valid one for programming the device in the unlock bypass mode. the unlock bypass reset command sequence is the only valid command sequence to exit the unl ock bypass mode. the unlock bypass reset command sequence consists of two bus cycles. the first cycle must contain the data (90h). the second cycle contain s only the data (00h). then, the device returns to the read mode. chip erase to erase a chip is to write 1 s into the entire memory array by executing the inte rnal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is wr itten after first two "unlock" cycles. then, there are two more write cycles prior to writing the chip erase command. the in ternal erase routine automatical ly pre-programs and verifies t he entire memory for an all zero data pattern prior to erasi ng. the automatic erase begins on the rising edge of the last we or ce pulse in the command sequence and terminates when dq7 is "1 ". after that the device returns to the read mode. figure 5. chip erase command sequence we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h 80h 555h chip erase start dq15-dq0 aaah 2aah/ 555h aah 55h 10h ry/by 555h/ aaah a19 a0(x16)/ a19 a-1(x8) block erase to erase a block is to write 1 s into the desired memory block by executing the in ternal erase routine. the block erase requires six bus cycles to write the command sequence shown in table 8. afte r the first two "unlock" cycles, the erase setup command (80h) i s written at the third cycle. then there ar e two more "unlock" cycles followed by the block erase command. the internal erase rou tine automatically pre-programs and verifies the entire memory prio r to erasing it. the block addres s is latched on the falling edge of we or ce , while the block erase command is latched on the rising edge of we or ce . multiple blocks can be erased sequentially by writing the six bus-cycle operation in figure 6. upon completion of the last cycl e for the block erase, additional block addr ess and the block erase command (30h) can be wri tten to perform the multi-block erase. an 50 s (typical) "time window" is required between the block erase command writes. the block erase command must be written within the 50 s "time window", otherwise the block erase command will be ignored. the 50 s "time window" is reset when the falling edge of the we occurs within the 50 s of "time window" to latch the block erase command. during the 50 s of "time window", any command other than the block erase or the erase suspend command written to the device will reset the device to read mode. after the 50 s of "time window", the block erase command will initiate the internal erase routine to erase the selected blocks. any block erase address and command following the exceeded "time window" may or may not be accepted. no other commands will be recognized except the erase suspend command during block erase operation.
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 13 we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h 80h 555h/ block erase start dq15-dq0 aaah 2aah/ 555h block address aah 55h 30h ry/by we dq15-dq0 figure 7. erase suspend/resume command sequence erase suspend / resume the erase suspend command interrupts the block erase to read or program data in a block that is not being erased. the erase sus - pend command is only valid during the block eras e operation including the time window of 50 s. the erase suspend command is not valid while the chip erase or the internal program routine sequence is running. when the erase suspend command is written during a bloc k erase operation, the device requires a maximum of 20 s to suspend the erase operation. but, when the erase suspend command is written during the block erase time window (50 s) , the device imme- diately terminates the block erase time window and suspends the erase operation. after the erase operation has been suspended, the device is availble for reading or programming data in a block that is not bei ng erased. the system may also write the autoselect comm and sequence when the device is in the erase suspend mode. when the erase resume command is executed, the block erase oper ation will resume. when the erase suspend or erase resume command is executed, the addresses are in don't care state. figure 6. block erase command sequence a19 a0(x16)/ a19 a-1(x8) a19 a0(x16)/ a19 a-1(x8) 555h/ aaah block address aah 30h xxxh erase resume xxxh b0h 30h erase suspend block erase start block erase command sequence
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 14 read while write the k8d1716u provides dual bank memory architecture that di vides the memory array into two banks. the device is capable of reading data from one bank and writing data to the other bank simu ltaneously. this is so called the read while write operation with dual bank architecture; this feature prov ides the capability of executing the read operation during program/erase or erase-susp end- program operation. the read while write operation is prohibited during the chip eras e operation. it is also allowed during erase operation when ei ther single block or multiple blocks from same bank are loaded to be erased. it means that the read while write operation is prohibi ted when blocks from bank1 and another blocks from bank2 ar e loaded all together for the multi-block erase operation. block group protection & unprotection the k8d1716u feature hardware block group protection. this featur e will disable both program and erase operations in any combi- nation of twenty five block groups of memory. please refer to t ables 10 and 11. the block group protection feature is enabled u sing programming equipment at the user?s site. the devic e is shipped with all block groups unprotected. this feature can be hardware protected or unprotected. if a block is protected, program or erase command in the protected block will be ignored by the device. the protected block can only be read. this is useful method to preserve an important program data. th e block group unprotection allows the protected blocks to be erased or programed. all blocks must be protected before unprotect o per- ation is executing. the block group protection and unprotection can be implemented by two methods. the first method needs the following conditions. operation ce oe we byte a9 a6 a1 a0 dq15/ a-1 dq8/ dq14 dq0/ dq7 reset block group protect l h l x x l h l x x d in v id block group unprotect l h l x x h h l x x d in v id the k8d1716u needs the recovery time (20 s) from the rising edge of we in order to execute its program, erase and read opera- tions. operation ce oe we byte a9 a6 a1 a0 dq15/ a-1 dq8/ dq14 dq0/ dq7 reset block group protect l v id xv id lhl x x x h block group unprotect l v id xv id hhl x x x h a9 oe don ' t care we address don ' t care 500ns 500ns block group address* figure 8. block group protect sequence (the second method) block group protect:150 s block group unprotect:500ms notes : * block group address is don't care during block group unprotection. address must be inputted to the block group address (a12~a19) during block group protection operation. please refer to figure 9 (algorithm) and switching waveforms of block group protect & unprotect operations. the second method needs the following conditions in order to keep backward compatibility. please refer to figure 8. low v id v id
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 15 figure 9. block group protection & unprotection algorithms block protect algorithm set up block group address block group protect: write 60h to block group address with a6=0,a1=1 a0=0 wait 150 s verify block group protect:write 40h to block group address with a6=0, a1=1,a0=0 read from block group address with a6=0, a1=1,a0=0 data=01h? protect another block group? remove v id from reset write reset command end wait 1 s first write cycle=60h? temporary block group unprotect mode block group unprotect write 60h with a6=1,a1=1 a0=0 wait 15ms verify block group unprotect:write 40h to block group address with a6=1, a1=1,a0=0 read from block group address with a6=1, a1=1,a0=0 data=00h? last block group remove vid from reset write reset command end no increment count count =1000? device failed no yes yes no no yes algorithm increment count count =25? device failed no yes no all block groups protected ? no block group , i= 0 start count = 1 reset =v id yes yes yes no note : all blocks must be protected bef ore unprotect operation is executing. verified ? block group protection ? yes no yes set up next block reset count=1 block unprotect group address
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 16 table 10. block group address (top boot block) block group block address block a19 a18 a17 a16 a15 a14 a13 a12 bga0 0 0 0 0 0 x x x ba0 bga1 0 0 0 01 x x x ba1 to ba3 10 11 bga2 0 0 1 x x x x x ba4 to ba7 bga3 0 1 0 x x x x x ba8 to ba11 bga4 0 1 1 x x x x x ba12 to ba15 bga5 1 0 0 x x x x x ba16 to ba19 bga6 1 0 1 x x x x x ba20 to ba23 bga7 1 1 0 x x x x x ba24 to ba27 bga8 11100xxx ba28 to ba30 11101xxx 11110xxx bga9 11111000 ba31 bga10 1 1 1 1 1 0 0 1 ba32 bga11 1 1 1 1 1 0 1 0 ba33 bga12 1 1 1 1 1 0 1 1 ba34 bga13 1 1 1 1 1 1 0 0 ba35 bga14 1 1 1 1 1 1 0 1 ba36 bga15 1 1 1 1 1 1 1 0 ba37 bga16 1 1 1 1 1 1 1 1 ba38
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 17 table 11. block group address (bottom boot block) block group block address block a19 a18 a17 a16 a15 a14 a13 a12 bga0 00000000 ba0 bga1 00000001 ba1 bga2 00000010 ba2 bga3 00000011 ba3 bga4 00000100 ba4 bga5 00000101 ba5 bga6 00000110 ba6 bga7 00000111 ba7 bga8 0 0 0 11 x x x ba8 to ba10 10 01 bga9 0 0 1 x x x x x ba11 to ba14 bga10 0 1 0 x x x x x ba15 to ba18 bga11 0 1 1 x x x x x ba19 to ba22 bga12 1 0 0 x x x x x ba23 to ba26 bga13 1 0 1 x x x x x ba27 to ba30 bga14 1 1 0 x x x x x ba31 to ba34 bga15 1 1 1 00 x x x ba35 to ba37 01 10 bga16 1 1 1 1 1 x x x ba38
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 18 temporary block group unprotect the protected blocks of the k8d1716u can be te mporarily unprotected by applying high voltage (v id = 8.5v~12.5v) to the reset pin. in this mode, previously protected blocks can be programmed or erased with the program or erase command routines. when the reset pin goes high (reset = v ih ), all the previously protected bloc ks will be protected again. if the wp /acc pin is asserted at v il , the two outermost boot blocks remain protected. reset program & erase operation v id v = v ih or v il at protected block ce we figure 10. temporary block group unprotect sequence secode(security code) block region the secode block feature provides a flash memory region to be stored unique and permanent identification code, that is, electro nic serial number (esn), customer code and so on. this is primar ily intended for customers who wish to use an electronic serial nu m- ber (esn) in the device with the esn protec ted against modification. once the secode bl ock region is protected, any further mod ifi- cation of that region is impossible. th is ensures the security of the esn once the product is shipped to the field. the secode block is factory locked or customer lockable. before the device is shipped, the factory locked secode block is writt en on the special code and it is protected. t he secode indicator bit (dq7) is permanently fixed at "1" and it is not changed. the customer lockable secode block is unprotected, ther efore it is programmed and erased. the secode indicator bit (dq7) of it is permanentl y fixed at "0" and it is not changed. but once it is protect ed, there is no procedure to unprotect and modify the secode block. the secode block region is 64k bytes in length and is accessed through a new command sequence (see table 8). after the system has written the enter secode block command sequence, the sy stem may read the secode block region by using the same addresses of the boot blocks (8kbx8). t he k8d1716ut occupies the address of the byte mode 3f0000h to 3fffffh (word mode 1f8000h to 1fffffh) and the k8d1716ub type occupies the address of the byte mode 000000h to 00ffffh (word mode 000000h to 007fffh). this mode of operation continues until th e system issues the exit sec ode block command sequence, or until power is removed from the device. on power-up, or foll owing a hardware reset, the device reverts to read mode. write protect (wp ) the wp /acc pin has two useful functions. the one is that certain boot block is protecte d by the hardware method not to use v id . the other is that program operation is accelerated to reduce the program time (refer to accelerated program operation paragraph ). when the wp /acc pin is asserted at v il , the device can not perform program and eras e operation in the two "outermost" 8k byte boot blocks independently of whether those bloc ks were protected or unprotected using t he method described in "block group pro- tection/unprotection". the write protected blocks can only be read. this is useful method to preserve an important program data. the two outermost 8k byte boot blocks ar e the two blocks containing the lowest addr esses in a bottom-boot-configured device, or the two blocks containing the highest addresses in a top-boot-congfigured device. (k8d1716ut : ba37 and ba38, k8d1716ub : ba0 and ba1) when the wp /acc pin is asserted at v ih , the device reverts to whether the two outermost 8k byte boot blocks were last set to be protected or unprotected. that is, block protection or unprotec tion for these two blocks depends on whether they were last prot ected or unprotected using the method described in "block group protection/unprotection". recommend that the wp /acc pin must not be in the state of floating or unc onnected, or the device may be led to malfunction.
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 19 accelerated program operation accelerated program operation reduces the program time . this is one of two functions provided by the wp /acc pin. when the wp / acc pin is asserted as v hh , the device automatically enters the aforementi oned unlock bypass mode, temporarily unprotecting any protected blocks, and reduces the program operation time. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp /acc pin returns the device to normal operation. recommend that the wp /acc pin must not be asserted at v hh except accelerated program operation, or the device may be damaged. in addition, the wp /acc pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunc- tion. software reset the reset command provides that the bank is reseted to read mode or erase-suspend-read mode. the addresses are in don't care state. the reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a pro- gram command sequence before programming begins. this resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. also, the reset command is valid between the sequence cycles in an autoselect command sequence. in the autosele ct mode, the reset command returns the bank to read mode. if a bank entered the autoselect mode in the erase suspend mode, the reset command returns the bank to erase-suspend-read mode. if dq5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the erase suspend state. hardware reset the k8d1716u offers a reset feature by driving the reset pin to v il . the reset pin must be kept low (v il ) for at least 500ns. when the reset pin is driven low, any operation in progress will be term inated and the internal state machine will be reset to the standby mode after 20 s. if a hardware reset occurs during a program operation, the data at that particular location will be lost. once the reset pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. also, note that all the data output pins are tri-stated for the duration of the reset pulse. the reset pin may be tied to the system reset pin. if a system rese t occurs during the internal program and erase routine, the device will be automatically reset to the r ead mode ; this will enable the systems micr oprocessor to read the boot-up firmware from the flash memory. power-up protection to avoid initiation of a write cycle during vcc power-up, reset low must be asserted during power-up. after reset goes high, the device is reset to the read mode. low vcc write inhibit to avoid initiation of a write cycle duri ng vcc power-up and power-down, a write cycle is locked out for vcc less than 1.8v. if vcc < v lko (lock-out voltage), the command register and all internal program /erase circuits are disabled. under this condition the device will reset itself to the read mode. subsequent writes will be ignored until the vcc level is greater than v lko . it is the user s responsi- bility to ensure that the control pins are logically correct to prevent unint entional writes when vcc is above 1.8v. write pulse glitch protection noise pulses of less than 5ns(typical) on ce , oe , or we will not initiate a write cycle. logical inhibit writing is inhibited under any one of the following conditions : oe = v il , ce = v ih or we = v ih . to initiate a write, ce and we must be "0", while oe is "1". commom flash memory interface common flash momory interface is contrived to increase the compatibility of host system software. it provides the specific inf orma- tion of the device, such as memory size, byte/word configurati on, and electrical features. once this information has been obtai ned, the system software will know which command sets to use to enable flash writes, block erases , and control the flash component. when the system writes the cfi command(98h) to address 55h in word mode(or address aah in byte mode), the device enters the cfi mode. and then if the system writes the address shown in table 12, the system can read the cfi data. query data are always presented on the lowest-order data outputs(dq0-7) only. in word(x16) mode, the upper data outputs(dq8-15) is 00h. to terminate this operation, the system must write the reset command.
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 20 table 12. common flash me mory interface code description addresses (word mode) addresses (byte mode) data query unique ascii string "qry" 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h primary oem command set 13h 14h 26h 28h 0002h 0000h address for primary extended table 15h 16h 2ah 2ch 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 2eh 30h 0000h 0000h address for alternate oem ex tended table (00h = none exists) 19h 1ah 32h 34h 0000h 0000h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 36h 0027h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 38h 0036h vpp min. voltage(00h = no vpp pin present) 1dh 3ah 0000h vpp max. voltage(00h = no vpp pin present) 1eh 3ch 0000h typical timeout per single byte/word write 2 n us 1fh 3eh 0004h typical timeout for min. size buffer write 2 n us(00h = not supported) 20h 40h 0000h typical timeout per individual block erase 2 n ms 21h 42h 000ah typical timeout for full chip erase 2 n ms(00h = not supported) 22h 44h 0000h max. timeout for byte/word write 2 n times typical 23h 46h 0005h max. timeout for buffer write 2 n times typical 24h 48h 0000h max. timeout per individual block erase 2 n times typical 25h 4ah 0004h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 4ch 0000h device size = 2 n byte 27h 4eh 0015h flash device interface description 28h 29h 50h 52h 0002h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 54h 56h 0000h 0000h number of erase block r egions within device 2ch 58h 0002h erase block region 1 information 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 2 information 31h 32h 33h 34h 62h 64h 66h 68h 0007h 0000h 0020h 0000h erase block region 3 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 4 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 21 table 12. common flash memory interface code note : 1. the number of blocks in bank2 is device dependent. k8d1716u(8mb/8mb) = 10h (16blocks) description addresses (word mode) addresses (byte mode) data query-unique ascii string "pri" 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h major version number, ascii 43h 86h 0031h minor version number, ascii 44h 88h 0032h address sensitive unlock(bits 1-0) 0 = required, 1= not required silcon revision number(bits 7-2) 45h 8ah 0000h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 8ch 0002h block protect 0 = not supported, 1 = number of blocks in per group 47h 8eh 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 90h 0001h block protect/unprotect scheme 04=k8d1x16u mode 49h 92h 0004h simultaneous operation (1) 00 = not supported, xx = number of blocks in bank2 4ah 94h 00xxh burst mode type 00 = not supported, 01 = supported 4bh 96h 0000h page mode type 00 = not supported, 01 = 4 word page 02 = 8 word page 4ch 98h 0000h acc(acceleration) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4dh 9ah 0085h acc(acceleration) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4eh 9ch 0095h top/bottom boot block flag 02h = bottom boot device, 03h = top boot device 4fh 9eh 000xh
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 22 device status flags the k8d1716u has means to indicate its status of operation in the bank where a program or erase operation is in processes. address must include bank address being excuted internal routine operation. the status is indicated by raising the device statu s flag via corresponding dq pins or the ry/ by pin. the corresponding dq pins are dq7, dq6, dq5, dq3 and dq2. the statuses are as follows : table 13. hardware sequence flags notes : 1. dq2 will toggle when the device performs successive read operations from the erase suspended block. 2. if dq5 is high (exceeded timing limits), successive reads from a problem block will cause dq2 to toggle. status dq7 dq6 dq5 dq3 dq2 ry/by in progress programming dq7 toggle 0 0 1 0 block erase or chip erase 0 toggle 0 1 toggle 0 erase suspend read erase suspended block 1100 toggle (note 1) 1 erase suspend read non-erase sus- pended block data data data data data 1 erase suspend program non-erase sus- pended block dq7 toggle 0 0 1 0 exceeded time limits programming dq7 toggle 1 0 no toggle 0 block erase or chip erase 0 toggle 1 1 (note 2) 0 erase suspend program dq7 toggle 1 0 no toggle 0 dq7 : data polling when an attempt to read the device is made while executing the inter nal program, the complement of the data is written to dq7 a s an indication of the routine in progress. when the routine is co mpleted an attempt to access to the device will produce the tru e data written to dq7. when a user attempts to read the device during the erase operation, dq7 will be low. if the device is placed in the erase suspend mode, the status can be detected via the dq7 pin. if the system tries to read an address which belongs to a block that is being erased, dq7 will be high. if a non-erased block addr ess is read, the device will produce the true data to dq7. if an attempt is made to program a protected block, dq7 outputs complements the data for approximately 1 s and the device then returns to the read mode without changing data in the block. if an attemp t is made to erase a protected block, dq7 outputs complement data in approximately 100us and the device then returns to the read mode without erasing the data in the block. dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or completed. once the device is at a busy st ate, dq6 will toggle. toggling dq6 will stop afte r the device completes its internal routi ne. if the device is in the erase suspend mode, an attempt to read an address that belongs to a block that is being erased will produce a high output of dq6. if an address bel ongs to a block that is not being erased, toggli ng is halted and valid data is produced at dq6. if an attempt is made to program a protected block, dq6 toggl es for approximately 1us and the device then returns to the read mode without changing the data in the block. if an attempt is m ade to erase a protected block, dq6 toggles for approximately 10 0 s and the device then returns to the read mode without erasing the data in the block. dq5 : exceed timing limits if the internal program/erase routine extends beyond the timi ng limits, dq5 will go high, indicating program/erase failure.
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 23 ry/by : ready/busy the k8d1716u has a ready / busy output that indicates either the completion of an op eration or the status of internal algorithms. if the output is low, the device is busy with either a program or an erase operation. if the output is high, the device is ready t o accept any read/write or erase operation. when the ry/ by pin is low, the device will not acc ept any additional program or erase commands with the exception of the erase suspend command. if the k8d1716u is placed in an erase suspend mode, the ry/ by output will be high. for programming, the ry/ by is valid (ry/ by = 0) after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, ry/ by is also valid after the rising edge of we pulse in the six write pulse sequence. for block erase, ry/ by is also valid after the rising edge of the sixth we pulse. the pin is an open drain output, allowing two or more ready/ busy outputs to be or-tied. an appropriate pull-up resistor is required for proper operation. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 pin. dq3 will go high if 50 s of the block erase time win- dow expires. in this case, the internal erase routine will init iate the erase operation.therefore, the device will not accept f urther write commands until the erase operation is complete d. dq3 is low if the block erase time wi ndow is not expired. within the block era se time window, an additional block erase comm and (30h) can be accepted. to confirm that the block erase command has been accepted, the software may check the status of dq3 following each block erase command. dq2 : toggle bit 2 the device generates a toggling pulse in dq2 only if an internal erase routine or an erase suspend is in progress. when the dev ice executes the internal erase routine, dq2 toggles only if an eras ing block is read. although the in ternal erase routine is in th e exceeded time limits, dq2 toggles only if an erasing block in the exceeded time limits is read. when the device is in the erase suspend mode, dq2 toggles only if an address in the erasing bl ock is read. if a non-erasing block address is read during the er ase suspend mode, then dq2 will produce valid data. dq2 will go high if the user tries to program a non-erase suspend block while t he device is in the erase suspend mode. combination of the status in dq6 and dq2 can be used to distinguish the erase operation from the program operation. vcc f ready / busy open drain output device vss where i l is the sum of the input currents of all devices tied to the ready / busy ball. rp rp = vcc f (max.) - v ol (max.) i ol + i l = 3.2v 2.1ma + i l
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 24 start dq7 = data ? no dq5 = 1 ? fail pass start dq6 = toggle ? no dq5 = 1 ? dq6 = toggle ? fail pass no no yes yes yes yes figure 13. temporary block group unprotect routine start reset =v id notes : 1. all protected block groups are unprotected. ( if wp /acc = v il , the two outermost boot blocks remain protected ) 2. all previously protected blo ck groups are protected once again. (note 1) perform erase or program operations temporary block unprotect completed (note 2) reset =v ih figure 11. data polling algorithms figure 12. toggle bit algorithms dq7 = data ? no yes no yes
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 25 dc characteristics recommended operating conditions ( voltage reference to vss ) parameter symbol min typ. max unit supply voltage v cc 2.7 3.0 3.6 v supply voltage v ss 000v absolute maximum ratings notes : 1. minimum dc voltage is -0.5v on input/ output pins. during tr ansitions, this level may fall to -2.0v for periods <20ns. maxim um dc voltage on input / output pins is vcc+0.5v which, during transitions, may overshoot to vcc+2.0v for periods <20ns. 2. minimum dc voltage is -0.5v on a9, oe , reset and wp /acc pins. during transitions, this level may fall to -2.0v for periods <20ns. maximum dc voltage on a9, oe , reset pins is 12.5v which, duri ng transitions, may overshoot to 14.0v for periods <20ns. 3. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. ex posure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss vcc vcc -0.5 to +4.0 v a9, oe , reset v in -0.5 to +12.5 wp /acc -0.5 to +12.5 all other pins -0.5 to +4.0 temperature under bias commercial t bias -10 to +125 c industrial -40 to +125 storage temperature t stg -65 to +150 c short circuit output current i os 5ma operating temperature t a (commercial temp.) 0 to +70 c t a (industrial temp.) -40 to + 85 c parameter symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc , v cc =v ccmax ? 1.0 - + 1.0 a a9,oe ,reset input leakage current i lit v cc =v ccmax , a9,oe ,reset =12.5v - - 35 a wp /acc input leakage current i liw v cc =v ccmax , wp /acc=12.5v - - 35 a output leakage current i lo v out =v ss to v cc ,v cc =v ccmax ,oe =v ih ? 1.0 - + 1.0 a active read current (1) i cc 1ce =v il , oe =v ih 5mhz - 14 20 ma 1mhz - 3 6 active write current (2) i cc 2ce =v il , oe =v ih, we =v il -1530ma read while program current (3) i cc 3ce =v il , oe =v ih -2550ma read while erase current (3) i cc 4ce =v il , oe =v ih -2550ma program while erase suspend current i cc 5ce =v il , oe =v ih -1535ma acc accelerated program current i acc ce =v il , oe =v ih acc pin -510 ma vcc pin -1530 standby current i sb 1 v cc =v ccmax ,ce , reset =v cc 0.3v wp /acc= v cc 0.3v or vss 0.3v -518 a standby current during reset i sb 2 v cc =v ccmax , reset =vss 0.3v, wp /acc=v cc 0.3v or vss 0.3v -518 a automatic sleep mode i sb 3 v ih =v cc 0.3v, v il =v ss 0.3v, oe =v il, i ol =i oh =0 -518 a input low level v il -0.5 - 0.8 v input high level v ih 0.7xvcc - v cc +0.3 v voltage for wp /acc block tempo- rarily unprotect and program accel- eration (4) v hh v cc = 3.0v 0.3v 8.5 - 12.5 v
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 26 ac characteristics ac test condition parameter value input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load c l = 30pf read operations note : 1. not 100% tested. parameter symbol v cc =2.7v~3.6v unit -7 -8 -9 min max min max min max read cycle time (1) t rc 70 - 80 - 90 - ns address access time t aa -70-80-90ns chip enable access time t ce -70-80-90ns output enable time t oe -25-25-35ns ce & oe disable time (1) t df -16-16-16ns output hold time from address, ce or oe (1) t oh 0 -0-0-ns notes : 1. the i cc current listed includes both the dc operating current and the frequency dependent component(at 5 mhz). the read current is typically 14 ma (@ vcc=3.0v , oe at vih.) 2. i cc active during internal routine(program or erase) is in progress. 3. i cc active during read while write is in progress. 4. the high voltage ( v hh or v id ) must be used in the range of vcc = 3.0v 0.3v 5. not 100% tested. 6. typical value are measured at vcc = 3.0v,t a =25 c , not 100% tested. capacitance (t a = 25 c, v cc = 3.3v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 10 pf output capacitance c out v out =0v - 10 pf control pin capacitance c in2 v in =0v - 10 pf parameter symbol test conditions min typ max unit voltage for autoselect and block protect (4) v id v cc = 3.0v 0.3v 8.5 - 12.5 v output low level v ol i ol =100 a, v cc =v ccmin --0.4v output high level v oh i oh =-100 a, vcc = v ccmin v cc -0.4 - - v low vcc lock-out voltage (5) v lko 1.8 - 2.5 v 0v vcc vcc/2 vcc/2 input pulse and test point input & output test point output load * cl= 30pf including scope c l device and jig capacitance
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 27 alternate we controlled write notes : 1. not 100% tested. 2. the duration of the program or erase operation varies and is calculated in the internal algorithms. parameter symbol v cc =2.7v~3.6v unit -7 -8 -9 min max min max min max write cycle time (1) t wc 70 - 80 - 90 - ns address setup time t as 0 - 0-0-ns t aso 55 - 55 - 55 - ns address hold time t ah 45 - 45 - 45 - ns t aht 0 - 0-0-ns data setup time t ds 35 - 35 - 45 - ns data hold time t dh 0 - 0-0-ns output enable setup time (1) t oes 0 - 0-0-ns output enable hold time read (1) t oeh1 0 - 0-0-ns toggle and data polling (1) t oeh2 10 - 10 - 10 - ns ce setup time t cs 0 - 0-0-ns ce hold time t ch 0 - 0-0-ns write pulse width t wp 35 - 35 - 45 - ns write pulse width high t wph 25 - 25 - 30 - ns programming operation word t pgm 14(typ.) 14(typ.) 14(typ.) s byte 9(typ.) 9(typ.) 9(typ.) s accelerated programming operation word t accpgm 9(typ.) 9(typ.) 9(typ.) s byte 7(typ.) 7(typ.) 7(typ.) s block erase operation (2) t bers 0.7(typ.) 0.7(typ.) 0.7(typ.) sec v cc set up time t vcs 50 - 50 - 50 - s write recovery time from ry/by t rb 0 - 0-0-ns reset high time before read t rh 50 - 50 - 50 - ns reset to power down time t rpd 20 - 20 - 20 - s program/erase valid to ry/by delay t busy 90 - 90 - 90 - ns v id rising and falling time t vid 500 - 500 - 500 - ns reset pulse width t rp 500 - 500 - 500 - ns reset low to ry/by high t rrb -20-20-20 s reset setup time for temporary unprotect t rsp 1 - 1-1- s reset low setup time t rsts 500 - 500 - 500 - ns reset high to address valid t rstw 200 - 200 - 200 - ns read recovery time before write t ghwl 0 - 0-0-ns ce high during toggling bit polling t ceph 20 - 20 - 20 - ns oe high during toggling bit polling t oeph 20 - 20 - 20 - ns ac characteristics write(erase/program)operations
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 28 ac characteristics write(erase/program)operations alternate ce controlled writes notes : 1. not 100% tested. 2.this does not include the preprogramming time. parameter symbol v cc =2.7v~3.6v unit -7 -8 -9 min max min max min max write cycle time (1) t wc 70 - 80 - 90 - ns address setup time t as 0-0-0-ns address hold time t ah 45 - 45 - 45 - ns data setup time t ds 35 - 35 - 45 - ns data hold time t dh 0-0-0-ns output enable setup time (1) t oes 0-0-0-ns output enable hold time read (1) t oeh1 0-0-0-ns toggle and data polling (1) t oeh2 10 - 10 - 10 - ns we setup time t ws 0-0-0-ns we hold time t wh 0-0-0-ns ce pulse width t cp 35 - 35 - 45 - ns ce pulse width high t cph 25 - 25 - 30 - ns programming operation word t pgm 14(typ.) 14(typ.) 14(typ.) s byte 9(typ.) 9(typ.) 9(typ.) s accelerated programming operation word t accpgm 9(typ.) 9(typ.) 9(typ.) s byte 7(typ.) 7(typ.) 7(typ.) s block erase operation (2) t bers 0.7(typ.) 0.7(typ.) 0.7(typ.) sec byte switching low to output high-z t flqz 25 - 25 - 30 - ns erase and program performance notes : 1. 25 c, v cc = 3.0v 100,000 cycles, typical pattern . 2. system-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte . in the preprogramming step of the internal erase routine, all bytes are programmed to 00h before erasure. parameter limits unit comments min typ max block erase time - 0.7 15 sec excludes 00h programming prior to erasure chip erase time - 25 - sec word programming time - 14 330 s excludes system-level overhead byte programming time - 9 210 s excludes system-level overhead accelerated byte/word program time word mode - 9 210 s excludes system-level overhead byte mode - 7 150 s excludes system-level overhead chip programming time word mode - 14 42 sec excludes system-level overhead byte mode - 18 54 sec erase/program endurance 100,000 - - cycles minimum 100,000 cycles guaran- teed
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 29 read operations switching waveforms oe address t ce t oeh1 ce outputs we high-z output valid t rc address stable t aa t oe t oh high-z t df ry/by high note : 1. not 100% tested. parameter symbol -7 -8 -9 unit min max min max min max read cycle time t rc 70 - 80 - 90 - ns address access time t aa -70-80-90ns chip enable access time t ce -70-80-90ns output enable time t oe -25-25-35ns ce & oe disable time (1) t df -16-16-16ns output hold time from address, ce or oe t oh 0-0-0-ns oe hold time t oeh1 0-0-0-ns
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 30 hardware reset/read operations switching waveforms parameter symbol -7 -8 -9 unit min max min max min max read cycle time t rc 70 - 80 - 90 - ns address access time t aa -70-80-90ns chip enable access time t ce -70-80-90ns output hold time from address, ce or oe t oh 0-0-0-ns reset pulse width t rp 500 - 500 - 500 - ns reset high time before read t rh 50 - 50 - 50 - ns reset address ce outputs high-z t rc address stable t aa t ce t oh t rh t rh t rp output valid
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 31 alternate we controlled program operations switching waveforms notes : 1. dq7 is the output of the complement of the data written to the device. 2. dout is the output of the data written to the device. 3. pa : program address, pd : program data 4. the illustration shows the last two cycles of the program command sequence. oe address t cs ce data we t ah t oh t df t as t rc t oe t ce t ds t dh t wp t oes t pgm status dout 555h pa pa a0h data polling t ch pd t wph ry/by t busy t rb t wc parameter symbol -7 -8 -9 unit min max min max min max write cycle time t wc 70 - 80 - 90 - ns address setup time t as 0-0-0-ns address hold time t ah 45 - 45 - 45 - ns data setup time t ds 35 - 35 - 45 - ns data hold time t dh 0-0-0-ns ce setup time t cs 0-0-0-ns ce hold time t ch 0-0-0-ns oe setup time t oes 0-0-0-ns write pulse width t wp 35 - 35 - 45 - ns write pulse width high t wph 25 - 25 - 30 - ns programming operation word t pgm 14(typ.) 14(typ.) 14(typ.) us byte 9(typ.) 9(typ.) 9(typ.) us accelerated programming operation word t accpgm 9(typ.) 9(typ.) 9(typ.) s byte 7(typ.) 7(typ.) 7(typ.) s read cycle time t rc 70 - 80 - 90 - ns chip enable access time t ce -70-80-90ns output enable time t oe -25-25-35ns ce & oe disable time t df -16-16-16ns output hold time from address, ce or oe t oh 0-0-0-ns program/erase valide to ry/by delay t busy 90 - 90 - 90 - ns recovery time from ry/by t rb 0-0-0-ns
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 32 alternate ce controlled program operations switching waveforms notes : 1. dq7 is the output of the complement of the data written to the device. 2. dout is the output of the data written to the device. 3. pa : program address, pd : program data 4. the illustration shows the last two cycles of the program command sequence. oe address we data ce t ah t as t ds t dh t cp t oes a0h 555h pa pa status dout data polling t cph t ws t pgm ry/by t busy t rb pd t wc parameter symbol -7 -8 -9 unit min max min max min max write cycle time t wc 70 - 80 - 90 - ns address setup time t as 0-0-0-ns address hold time t ah 45 - 45 - 45 - ns data setup time t ds 35 - 35 - 45 - ns data hold time t dh 0-0-0-ns oe setup time t oes 0-0-0-ns we setup time t ws 0-0-0-ns we hold time t wh 0-0-0-ns ce pulse width t cp 35 - 35 - 45 - ns ce pulse width high t cph 25 - 25 - 30 - ns programming operation word t pgm 14(typ.) 14(typ.) 14(typ.) s byte 9(typ.) 9(typ.) 9(typ.) s accelerated programming operation word t accpgm 9(typ.) 9(typ.) 9(typ.) s byte 7(typ.) 7(typ.) 7(typ.) s program/erase valide to ry/by delay t busy 90 - 90 - 90 - ns recovery time from ry/by t rb 0-0-0-ns
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 33 switching waveforms parameter symbol -7 -8 -9 unit min max min max min max chip enable access time t ce -70-80-90ns ce to byte switching low or high t elfl /t elfh -5-5-5ns byte switching low to output high-z t flqz -25-25-30ns byte switching high to output active t fhqv -25-25-35ns oe t flqz ce dq0-dq7 byte we byte timing diagram for write operation the falling edge of the last we signal ce byte t hold (t ah ) dq15/a-1 t elfl address input (a-1) t set (t as ) word to byte timing diagram for read operation byte to word timing diagram for read operation data output (dq0-dq7) dq8-dq14 data output (dq8-dq14) data output (dq15) oe t fhqv ce dq0-dq7 byte dq15/a-1 t elfh data output dq8-dq14 address input (a-1) data output (dq8-dq14) (dq15) t ce t ce data output (dq0-dq7)
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 34 switching waveforms chip/block erase operations parameter symbol -7 -8 -9 unit min max min max min max write cycle time t wc 70 - 80 - 90 - ns address setup time t as 0-0-0-ns address hold time t ah 45 - 45 - 45 - ns data setup time t ds 35 - 35 - 45 - ns data hold time t dh 0-0-0-ns oe setup time t oes 0-0-0-ns ce setup time t cs 0-0-0-ns write pulse width t wp 35 - 35 - 45 - ns write pulse width high t wph 25 - 25 - 30 - ns read cycle time t rc 70 - 80 - 90 - ns v cc set up time t vcs 50 - 50 - 50 - s oe address t cs ce data we t ah t as t rc t ds t dh 80h aah aah 55h 30h 10h for chip erase 555h 2aah 555h 555h 2aah ba 555h for chip erase t wph t wp t oes 55h ry/by t wc t vcs vcc note : ba : block address
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 35 read while write operations switching waveforms parameter symbol -7 -8 -9 unit min max min max min max write cycle time t wc 70 - 80 - 90 - ns write pulse width t wp 35 - 35 - 45 - ns write pulse width high t wph 25 - 25 - 30 - ns address setup time t as 0-0-0-ns address hold time t ah 45 - 45 - 45 - ns data setup time t ds 35 - 35 - 45 - ns data hold time t dh 0-0-0-ns read cycle time t rc 70 - 80 - 90 - ns chip enable access time t ce -70-80-90ns address access time t aa -70-80-90ns output enable access time t oe -25-25-35ns oe setup time t oes 0-0-0-ns oe hold time t oeh2 10 - 10 - 10 - ns ce & oe disable time t df -16-16-16ns address hold time t aht 0-0-0-ns ce high during toggle bit polling t ceph 20 - 20 - 20 - ns note : this is an example in the program-cas e of the read while write function. da1 : address of bank1, da2 : address of bank 2 pa = program address at one bank , ra = read address at the other bank, pd = program data in , rd = read data out oe ce dq we t rc read command command read read read t ah t aa t ce t as t aht t as t ceph t oe t oes t wp t oeh2 t df t ds t dh t df da1 da2 da1 da1 da2 da2 (555h) (pa) (pa) valid output valid output valid input valid output valid input status address (a0h) (pd) t rc t rc t rc t wc t wc
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 36 data polling during internal routine operation switching waveforms parameter symbol -7 -8 -9 unit min max min max min max program/erase valid to ry/by delay t busy 90 - 90 - 90 - ns chip enable access time t ce -70-80-90ns output enable time t oe -25-25-35ns ce & oe disable time t df -16-16-16ns output hold time from address, ce or oe t oh 0-0-0-ns oe hold time t oeh2 10 - 10 - 10 - ns oe t ce t oeh2 ce dq7 we t oe high-z t df note : *dq7=vaild data (the device has completed the internal operation). dq7 *dq7 = valid data t oh t pgm or t bers high-z valid data dq0-dq6 data in data in we ry/by timing diagram during program/erase operation the rising edge of the last we signal ce ry/by t busy entire progrming or erase operation status data
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 37 toggle bit during intern al routine operation switching waveforms t dh ce address* oe dq6/dq2 we ry/by data in t aht t aht t aso t as t ceph t oeh2 t oeph status data t o e status data status data array data out note : address for the write operation must include a bank address (a19) where the data is written. dq 6 we dq 2 enter embedded erasing erase suspend enter erase suspend program erase suspend program erase resume erase erase suspend read erase erase complete erase suspend read note : dq2 is read from the erase-suspended block. toggle dq 2 and dq 6 with oe or ce parameter symbol -7 -8 -9 unit min max min max min max output enable access time t oe -25-25-35ns oe hold time t oeh2 10 - 10 - 10 - ns address hold time t aht 0-0-0-ns address setup t aso 55 - 55 - 55 - ns address setup time t as 0-0-0-ns data hold time t dh 0-0-0-ns ce high during toggle bit polling t ceph 20 - 20 - 20 - ns oe high during toggle bit polling t oeph 20 - 20 - 20 - ns
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 38 reset timing diagram switching waveforms parameter symbol -7 -8 -9 unit min max min max min max reset pulse width t rp 500 - 500 - 500 - ns reset low to valid data (during internal routine) t ready -20-20-20 s reset low to valid data (not during internal routine) t ready - 500 - 500 - 500 ns reset high time before read t rh 50 - 50 - 50 - ns ry/by recovery time t rb 0-0-0-ns reset high to address valid t rstw 200 - 200 - 200 - ns reset low set-up time t rsts 500 - 500 - 500 - ns reset t rp power-up and reset timing diagram ce or oe ry/by t ready t rb reset ce or oe ry/by t rh t ready t rp reset timings not during internal routine reset timings during internal routine high reset t aa vcc address data t rsts
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 39 block group protect & unprotect operations switching waveforms ce temporary block group unprotect program or erase command sequence r eset we t rsp ry/by t vid v id v ss ,v il , or v ih v ss ,v il , or v ih t rrb t vid bga,a6 a1,a0 reset ce we data oe v ss ,v il , 60h 60h 40h status* block group protect / unprotect verify 1 s block group protect:150 s block group unprotect:15ms notes : block group protect (a6= v il , a1= v ih , a0= v il ) , status=01h block group unprotect (a6= v ih , a1= v ih , a0= v il ) , status=00h bga = block group address (a12 ~ a19) ry/by v id valid valid valid t busy t rb or v ih v ss ,v il , or v ih
flash memory k8d1716utb / k8d1716ubb revision 0.0 july 2004 40 package dimensions 48-pin lead plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8?c 0.010 0.25 typ 0.125 +0.075 -0.035 0.005 +0.003 -0.001 0.50 0.020 ()

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